Increasing numbers of integrated circuits (“chips”) feature system on chip (“SoC”) designs, where a number of different components are integrated onto a single chip. These components can include digital, analog, and mixed signal devices. SoC devices can be designed in various abstractions, including C/SystemC transaction accurate, C/SystemC cycle accurate, RTL, and gate abstractions. Often one part of the SoC is modeled in one level of abstraction, while another part is modeled in a different abstraction. This may be done for reasons of efficiency of model creation, accuracy, or performance. As an example, a CPU of the SoC may be best modeled at a SystemC transaction level for faster software code execution, while a sub-block of the SoC is modeled at an RTL level for cycle-accuracy. A SoC model created with more than one abstraction can be termed a “hybrid model.”
SoC devices are typically functionally verified prior to fabrication using hardware, software, or a combination of hardware and software specially designed to perform functional verification. Such functional verification devices can include simulators and emulators, both of which can be used to perform co-simulation of hybrid models. An immediate problem that arises out of this hybrid model is representation of shared system resources, such as memory. As an example, for fast CPU execution at the transaction level in SystemC simulation, the memory is typically best modeled in SystemC. However, for fast RTL emulation, the memory is typically best modeled as RTL.
The usage of system level memory in a SoC falls into three broad categories: (i) memory used exclusively by the operating system and user applications for running code and computations (software), (ii) memory used exclusively by SoC's input/output (I/O) blocks for their own storage, and (iii) memory shared between software and I/O blocks. The traditional approach to such shared memory space is to either keep memory as an entirely SystemC model (a “memory-out” approach from the point of view of RTL running in an emulator) or keep memory as entirely RTL (“memory-in” from the point of view of the emulator). In either case, there is significant overhead. In the memory-out case this is because of the RTL frequently accessing a SystemC memory through a RTL-to-SystemC transactor. In the memory-in case this is because of a CPU accessing the RTL memory through a SystemC-to-RTL transactor. This overhead results as the emulator needs to stop and synchronize to SystemC simulation to allow for each of these accesses. These frequent accesses are very inefficient for overall simulation performance of the model. As a result, the system simulation performance will be lower compared to either the all-virtual SystemC SoC model or the all-RTL SoC running in an emulator.
Memory models can also be created that provide native access in both a C/SystemC and RTL abstractions. In this model, two images for each memory are created, one in each abstraction. However, a problem with this topology is maintaining coherency between the two images of the same memory, for each of the memories.